RTimothyEdwards/contact_programmed_ROM_cells

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Created 6 months ago
Updated 5 months ago

RTimothyEdwards/contact_programmed_ROM_cells

RTimothyEdwards

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Set of layouts for contact-programmed ROM values of various bit widths.

magic

Magic VLSI Layout Tool

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

qflow

Qflow full end-to-end digital synthesis flow for ASIC designs

XCircuit

XCircuit circuit drawing and schematic capture tool

netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

qrouter

Qrouter detail router for digital ASIC designs

irsim

IRSIM switch-level simulator for digital circuits

capiche

Parasitic capacitance analysis of foundry metal stackups

ravenna_standalone

A lightweight version of the efabless Ravenna RISC-V processor chip design files for public access

tutorial_layout

Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.

caravel_openframe_project

Example digital project for the Efabless Caravel "openframe" harness

sky130_ef_ip__opamp

Instrumentation amplifier (analog IP example)

chaos_automaton

Chaos Automaton (efabless Caravel harness digital project)

tclftdi

Tcl/Tk console based test system for development boards with FTDI chips. Also supports GPIB and instrumentation over ethernet.

chipalooza_projects_1

Chipalooza challenge first test chip of projects

sky130_ef_ip__xtal_osc_32k

Low power, low speed (32.768kHz) crystal oscillator circuit for sky130 technology

sky130_ef_ip__samplehold

Analog 3.3V sample and hold circuit, with buffered output

sky130_ef_ip__rdac3v_8bit

8-bit resistor ladder DAC with 3.3V output range

sky130_ef_ip__cdac3v_12bit

12-bit capacitive DAC

vsd_lvs_lab

Laboratory exercises for the VSD course on physical verification, part 5: LVS

sky130_ef_ip__biasgen

Current bias generator circuit for distributing bias currents to analog circuits.

vsd_drc_lab

Laboratory exercises for the VSD course on physical verification, part 3, DRC

striVe_sky130

The striVe chip (test vehicle for sky130) picoRV32 implementation

sky130_ef_ip__ccomp3v

Continuous analog comparator, 1mV resolution

sky130_ef_ip__xtal_osc_16M

High speed (16MHz) crystal oscillator in sky130 technology

fracn_dll

Alternative version of the Caravel digital locked loop (DLL) with a fractional feedback divider

sky130_ef_ip__rc_osc_16M

16MHz (nominal) current-starved ring oscillator