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servo-motor
Servo motorVHDL
VDHLBoundaryScan
The boundary scan is implemented in VHDLimplementing-napoleon-cipher-in-hardware
smartsystemsproject-2019
Smart systems projectPartsVisionRecognitionwebsite
Swift
©2019 | All right reservedTCP_Client
Client server in C LanguageC-plus-plus-Code
Algorithms and Data Structures in C++systems-engineering
Report in Systems Design and Engineering plus take home examFPGA
en-decryption-algorithm
Ceasar cipher methodarray-sorting-in-HW-SW
We explored and implemented three different sorting algorithms as software (single-thread C programs) and hardware (VHDL) implementations in FPGAs. Furthermore, we compared the different implementations with regards to efficiency, performance, flexibility, resource usage and code complexity, while particular contrasting hardware and software trade-offs. We found that concurrent sorting algorithms can be parallelized in hardware to achieve higher performance, however hardware implementations require more development effort, have more code complexity and also require more hardware resources. Hence there is a trade-off to be made between multiplexing the algorithm in time or in space, depending on the context of the application.Love Open Source and this site? Check out how you can help us