Michaelvll/RISCV_CPU Michaelvll/RISCV_CPU

  • Stars
    star
    60
  • Rank 500,583 (Top 10 %)
  • Language
    C
  • License
    MIT License
  • Created almost 7 years ago
  • Updated almost 5 years ago
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Michaelvll/RISCV_CPU
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Michaelvll

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Repository Details

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

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