MaharshSuryawala/Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS MaharshSuryawala/Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS

  • Stars
    star
    4
  • Rank 3,304,323 (Top 66 %)
  • Language Verilog
  • License
    MIT License
  • Created about 5 years ago
  • Updated about 4 years ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
MaharshSuryawala/Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS
github

MaharshSuryawala

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.

More Repositories

1

Food-Image-Recognition

A system that takes food images as an input, recognizes the food automatically and gives the nutritional-facts as an output.
Jupyter Notebook
69
star
2

Face-Detection-and-Facial-Expression-Recognition

A systematic comparison of different machine learning & deep learning classification approaches applied to the problem of fully automatic recognition of Facial Expressions.
Jupyter Notebook
29
star
3

Predict-Disease-From-Symptoms

A Disease-Symptoms Network and a system that predicts diseases from symptoms using a decision tree classifier.
Jupyter Notebook
13
star
4

Image-Compression

Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
Verilog
13
star
5

Dual-Tone-Multi-Frequency-DTMF-Decoder

DTMF stands for Dual Tone Multiple Frequency, it's a telecommunication signaling system using voice-frequency band over telephone lines.
MATLAB
2
star
6

Heart-Disease-Risk-Prediction

A system that predicts the risk of heart diseases in patients using information such as chest pain, cholesterol, thalassemia, exercise-induced angina, ECG, etc.
HTML
1
star