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sEMG-Hand-Gesture-Recognition
The source code for the real-time hand gesture recognition algorithm based on Temporal Muscle Activation maps of multi-channel surface electromyography (sEMG) signals.DeepPhaseUnwrap
This repository Introduces a joint convolutional and spatial quad-directional LSTM (SQD-LSTM) network for phase unwrapping in 2D images.Schrodinger-Equation-Simulation
Includes the codes used for simulating the Schrรถdinger's Wave Equation in 1D, 2D and 3D potential wells.PPG-Pulse-Meter
The Real Time Photoplethysmographic Non - Invasive Pulse Meter was developed by Ashwin de Silva and Sachini Hewage, initially for the EXMO'2017 at the University of Moratuwa. The hardware component of the device currently make use of ATmega2560 chip and the Pulse Sensor Amped. (courtesy of https://www.sparkfun.com/products/11574) For the software base, arduino IDE and Processing IDE was used. Future developments of the project will be available when the results are well benchmarked.value-of-ood-data
The value of out-of-distribution data (ICML 2023)Curriculum-Vitae
Latest version of my CV.MCW2Graph
DeepRetina
Work on retinal and scleral image understanding (in progress)FIR-Filter-Design-
The project was conducted as a part of the module Digital Signal Processing EN2570. The objective was to design a Non - Recursive (Finite Impulse Response) Bandstop Filter using the Kaiser Window Function. MATLAB 2014a software package was used as the programming environment for the design project.IRIS
iris-plot is a tool written in MATLAB to visualize the gain of function or the loss of function in terms of the p-value from the two-sample unpaired t-test performed upon the patient and control data.UART-Implementation-on-FPGA
The Universal Asynchronous Receiver -Transmitter (UART) is a hardware device utilized for asynchronous serial communication between electronic devices. It obtains each byte (8 parallel bits) of data and converts it into a series of bits which are transmitted in a sequential manner. The objective was to implement a UART using a Field Programmable Gate Array (FPGA) and achieve half -duplex communication between two such UARTs. The device was tested using the test bench and the timing diagrams were obtained successfully.lipschitz-llm
ProL
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