Juanx65/RISC-V

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Language Verilog
Created over 1 year ago
Updated 3 months ago

Juanx65/RISC-V

Juanx65

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Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.

DeepDeconvV2

Deep Deconvolution for Seismic Waves with Real and Simulated Distributed Acoustic Sensing Data: State-of-the-Art Review

ConvSalmonModel

Identification of individual salmons using CNN and HoG approach

WifiSniffing

Testing A Case Study of WiFi Sniffing of Probe request

DeepDeconv

Deep Deconvolution for Seismic Waves with Real and Simulated Distributed Acoustic Sensing Data: State-of-the-Art Review

ArtTRT

Estado del arte de TensorRT

Jupyter Notebook

bill-detection

bill detection based on deep learning YOLOv3 / RetinaNet on a restfull service using flask with implementation on an android aplication using Android-SmartWebView repository

UNetSalmonModel

UNetTRT

estado del arte de TensorRT

yolov8test

learning how to do profiling on a yolov8 net using nvidia nsight compute

SalmonsTRT