• Stars
    star
    24
  • Rank 986,245 (Top 20 %)
  • Language
    Python
  • Created almost 13 years ago
  • Updated about 12 years ago

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Repository Details

A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. Targeted at the Rhino Project (see URL).