Chun-Feng/2015CA-Course-NCTU---MM

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Chun-Feng/2015CA-Course-NCTU---MM

Chun-Feng

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NCTU-2015 fall CA course final project task.

CACTI-6.0

ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write ports, and it can easily get the simulation result (like frequency, power consumption, and area... etc.).

CACTI-6.5

This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condition circumstance.

LVT_Writes_Method

Live Value Table (LVT-based) techniques is increasing write ports method, and using table to track the latest address data.

Block_RAM_Module_FPGAs

Block RAMs (BRAMs) provide two types: two ports or dual-ports mode on FPGAs.

2R1W-Memory-Design

Here offer 2R1W-based building block to proposed methodology to create multi-ported memory design. And different design to support more multi-ported level growth tree.