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AGEMA
Automated Generation of Masked HardwareAES_masked_BRAM
Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)BIKE
Contains HDL code for the PQC Key Encapsulation Mechanism BIKEVERICA
SILVER
SILVER - Statistical Independence and Leakage VerificationDL-LA
DL-LA: Deep Learning Leakage Assessment. Source Code and Traces.FIVER
KEM-NIZKPoP
Proof-of-possession for KEM certificates using verifiable generationecmongpu
ECM Factorization on CUDA-GPUsdilithium-artix7
Implementations for all round-3 parameter sets of the PQC signature scheme DilithiumLWC-Masking
RacingBIKE
NullFresh
Codes and designs of first-order SCA secure hardware implementations without fresh randomnessWrite-Write
PoC Code from the Paper "Write Me and I'll Tell You Secrets - Write-After-Write Effects On Intel CPUs"XMSS-LMS-HW-Agile
Code for the paper "Agile Acceleration of Stateful Hash-Based Signatures in Hardware"SPEEDY
Code repository for the SPEEDY family of ultra low-latency block ciphersXMSS-VHDL
Configurable Hardware Implementation of XMSSSAIREDA
Security-Aware Intermediate Representation and Electronic Design AutomationLow-Latency_Keccak
FrodoKEM
Hardware Implementation of FrodoKEMGHPC
Generic Hardware Private Circuitslattice-anonymous-credentials
HPC3
EASIMask
dilithium-faults
NullFresh2
Codes and designs of second-order SCA secure hardware implementations with almost no fresh randomnessLove Open Source and this site? Check out how you can help us