Archfx/V2G

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Language Verilog
Created about 4 years ago
Updated over 1 year ago

Archfx/V2G

Archfx

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Verilog variables descriptions to graphs converting tool

FPGA-stereo-Camera-Basys3

Integration of two camera 📷 modules to Basys 3 FPGA

RTK-NTRIP-RTCM

Contains program to Send RTCM3 📡 data to Hosted NTRIP server and fetch NTRIP data and display on another rover. Real time kinematic supported base and rover (Ublox-M8P) GPS units are required.

FPGA-DepthMap-Basys3

Real Time depth map 🏞️ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.

TrafficLightController

Design a sequential circuit (FSM) and implement using Verilog

FPGA_depthMap

Using stereo vision 👀 to identify the obstacles by processing images on a FPGA

Jupyter Notebook

StopWatch-Basys3

Stopwatch ⏱️ implemented using Verilog with Vivado

eKema

Machine learning for Paddy cultivation

AREST

Simple Greedy algorithm AREST, which can find you the best state encoding for a given FSM that is resistant against Laser Fault Injection (LFI) attacks.

Kobuki-Serial-Controller

Serial raw python implementation for controlling Kobuki Robot base

assert_NoC

Assertion based Network on Chip Security Implementation

sweetRV

sweetRV 🧁 is a SoC with a minimal RISC-V processor with firmware for IceSugar-Nano FPGA

ByteTorrent

DengAI

Solution to DengAI: Predicting Disease Spread HOSTED BY DRIVENDATA

Jupyter Notebook

DIY-PRM_01

Arduino PRM01 module for RadioLink At9 and At10

SnpsTools

Simple beginner tutorial for Synopsys tool chain

550_DRONE_CAD_PX4

3D model of the Final drone assembly for the Simulation

ProductCipher

Permutation and Random substitution text encryptor

NanoProcessor

A simple microprocessor (hence, called a nanoprocessor) created using ISE design suite capable of executing a simple set of instructions.