• Stars
    star
    9
  • Rank 1,939,727 (Top 39 %)
  • Language VHDL
  • License
    MIT License
  • Created over 5 years ago
  • Updated over 1 year ago

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Repository Details

Real Time depth map ๐Ÿž๏ธ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.

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