Discover AngeloJacobo/ULX3S_FPGA_Sobel_Edge_Detection

Stars
15
Rank 1,371,379 (Top 28 %)
Language Verilog
License
MIT License
Created about 3 years ago
Updated about 3 years ago

AngeloJacobo

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board

UberDDR3

Opensource DDR3 Controller

Verilog

165

FPGA_Book_Experiments

My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu

Verilog

RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Verilog

FPGA_OV7670_Camera_Interface

Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps

Verilog

OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

FPGA_RealTime_and_Static_Sobel_Edge_Detection

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Verilog

FPGA_SDRAM_Controller

SDRAM controller optimized to a memory bandwidth of 316MB/s

Verilog

DDR3-Notes

My notes for DDR3 SDRAM controller

ULX3S_FPGA_Camera_Streaming

Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board

Verilog

FPGA_Asynchronous_FIFO

FIFO implementation with different clock domains for read and write.

Verilog

FPGA_I2C_Implementation

Bit-bang i2c protocol for interfacing with DS1307 RTC

Verilog

Customize-Android-Apps

This contains my notes on how to customize existing Android apps such as changing app name, app icon, hiding app from the app drawer, and others.

SDCard_Driver_Test

Vivado files for testing my SD card driver. Implemented on CMOD S7 FPGA.

Verilog

Python_Scripts

Just a collection of my python scripts

Python

AngeloJacobo/ULX3S_FPGA_Sobel_Edge_Detection_OV7670

AngeloJacobo

Reviews

Repository Details

More Repositories