• Stars
    star
    1
  • Language
    Python
  • License
    MIT License
  • Created over 2 years ago
  • Updated over 2 years ago

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Repository Details

Just a collection of my python scripts

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SDRAM controller optimized to a memory bandwidth of 316MB/s
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ULX3S_FPGA_Sobel_Edge_Detection_OV7670

Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
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ULX3S_FPGA_Camera_Streaming

Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
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DDR3-Notes

My notes for DDR3 SDRAM controller
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FPGA_Asynchronous_FIFO

FIFO implementation with different clock domains for read and write.
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FPGA_I2C_Implementation

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Customize-Android-Apps

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SDCard_Driver_Test

Vivado files for testing my SD card driver. Implemented on CMOD S7 FPGA.
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