AmrMEid/AES-128-decryption-using-Verilog

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Language Verilog
Created about 4 years ago
Updated about 4 years ago

AmrMEid/AES-128-decryption-using-Verilog

AmrMEid

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designing hardware using Verilog to decrypt AES message and implement the design with less than 3% of zynq FPGA resources in one-lab CU competition

Digital-Design-Recap

A simple Recap for different Digital Design topics from different references and books.