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Restoring-Division
Restoring division for unsigned integer.Square-Shape-Detector
x and y are input signals representing the x and y coordinates, respectively, each being 1-bit wide.general_clk_div_by_odd
A general frequency divider by odd is a circuit or device used to divide the frequency of an input signal by an odd integer. The purpose of a frequency divider is to generate an output signal with a frequency that is a fraction of the input frequencyGlitch_free_clock_mux
The same logic function can occasionally be operated with multiple clock sources because of to clock multiplexing. This kind of reasoning may include errors that lead to functional issues.Programmable-Sequence-Detector2
Added extra signal to control sequence from user end with load functionality. Please refer Programmable Sequence Detector first.transitions_ckt
based on input data , find which 1->0 / 0->1 transition is more or equall.counting_number_of_1
Counting number of one's in a seven bit bus.uart_basic
divide_and_conquer_32x32
Divide and conquer :- Divide the 32 x 32 multiplication operation into smaller sub-tasks. For example, you can divide it into four 16 x 16 multiplications or sixteen 8 x 8 multiplications.min_max_without_comparator
designing a corcuit of MAX and MIN without using Comparator, when in > Max , out = Max ; in< Min , out = Min; Max<in<Min, out = in;frequency-divider--2f-3-
Design the Digital Circuit which gives fout = (2/3) fin.Glitch_clock_mux
When a modern chip is operating, it may occasionally be required to switch between two separate clocks. What would happen if we switched clocks using the standard mux?Divide-by-three
While going through your Grandma's old store, you come across an interesting machine which takes an input x and gives an output whenever the number formed within the machine is divisible by 3Single_Cycle_Arbiter
The module is designed to operate in a single-cycle fashion, providing fast and efficient arbitration for multiple request sources.Sequence_generator
Design the following sequence generator module: 0 → 1 → 1 → 1 → 2 → 2 → 3 → 4 → 5 → 7 → 9 → 12 → 16 → 21 → 28 → 37 → ... Assume the sequence goes on forever until the circuit is reset. All the flops should be positive edge triggered with asynchronous resets (if any).BCD
BCD circuit with a minimum logic.Clock_gating_cell
Clock gating is a technique used in synchronous circuits to reduce dynamic power dissipation and power wasted by digital circuits. It involves turning off the clock to certain parts of the digital design when not needed.Round-Robin-Arbiter-Fixed-Time-Sclices
Accessing a Memory location by multiple Processor. Arbiter takes four input requests and outputs a grant(ONE HOT ENCODED) signal.read_comments_as_HDL
using "AND" gate logic to test "read_comments_as_HDL" synthesis directivepalindrome_3bit
You are tasked to design a circuit which would detect a 3-bit palindrome sequence from incoming stream of bits.generic_count_1
Generic counting one's in a Bus.leading_1_detector
Design a leading "1" detector circuit for 8-bit busSPI
SPI is a synchronous communication protocol that transmits and receives information simultaneously with high data transfer rates and is designed for board-level communication over short distances. The SPI communication interface is advantageous when needing to communicate between multiple devices.Performance_Counter
This Verilog module named "counter" implements a configurable counter with a width parameter (WIDTH).Atomic-Counters
Question is in READMEPerfect_Square
This module is useful for generating perfect square values.Abhirecket
Div_5
Create a block that check if a number is divisible by “5” ? Every cycle, LSB receives a new bit; if the current sequence is divisible by “5”, block transmits “1”.fibanocci
The Fibonacci series is a sequence of numbers in which each number is the sum of the two preceding ones, usually starting with 0 and 1. So, the Fibonacci series begins as follows: 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233, 377, ...Love Open Source and this site? Check out how you can help us