Abhirecket/Divide-by-three Abhirecket/Divide-by-three

  • Stars
    star
    1
  • Language Verilog
  • Created about 1 year ago
  • Updated 8 months ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
Abhirecket/Divide-by-three
github

Abhirecket

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

While going through your Grandma's old store, you come across an interesting machine which takes an input x and gives an output whenever the number formed within the machine is divisible by 3

More Repositories

1

Restoring-Division

Restoring division for unsigned integer.
Verilog
2
star
2

Square-Shape-Detector

x and y are input signals representing the x and y coordinates, respectively, each being 1-bit wide.
Verilog
2
star
3

general_clk_div_by_odd

A general frequency divider by odd is a circuit or device used to divide the frequency of an input signal by an odd integer. The purpose of a frequency divider is to generate an output signal with a frequency that is a fraction of the input frequency
Verilog
2
star
4

Glitch_free_clock_mux

The same logic function can occasionally be operated with multiple clock sources because of to clock multiplexing. This kind of reasoning may include errors that lead to functional issues.
Verilog
2
star
5

Programmable-Sequence-Detector2

Added extra signal to control sequence from user end with load functionality. Please refer Programmable Sequence Detector first.
Verilog
1
star
6

transitions_ckt

based on input data , find which 1->0 / 0->1 transition is more or equall.
Verilog
1
star
7

counting_number_of_1

Counting number of one's in a seven bit bus.
Verilog
1
star
8

uart_basic

Verilog
1
star
9

divide_and_conquer_32x32

Divide and conquer :- Divide the 32 x 32 multiplication operation into smaller sub-tasks. For example, you can divide it into four 16 x 16 multiplications or sixteen 8 x 8 multiplications.
VHDL
1
star
10

min_max_without_comparator

designing a corcuit of MAX and MIN without using Comparator, when in > Max , out = Max ; in< Min , out = Min; Max<in<Min, out = in;
Verilog
1
star
11

frequency-divider--2f-3-

Design the Digital Circuit which gives fout = (2/3) fin.
Verilog
1
star
12

Glitch_clock_mux

When a modern chip is operating, it may occasionally be required to switch between two separate clocks. What would happen if we switched clocks using the standard mux?
Verilog
1
star
13

Single_Cycle_Arbiter

The module is designed to operate in a single-cycle fashion, providing fast and efficient arbitration for multiple request sources.
Verilog
1
star
14

Sequence_generator

Design the following sequence generator module: 0 → 1 → 1 → 1 → 2 → 2 → 3 → 4 → 5 → 7 → 9 → 12 → 16 → 21 → 28 → 37 → ... Assume the sequence goes on forever until the circuit is reset. All the flops should be positive edge triggered with asynchronous resets (if any).
Verilog
1
star
15

BCD

BCD circuit with a minimum logic.
Verilog
1
star
16

Clock_gating_cell

Clock gating is a technique used in synchronous circuits to reduce dynamic power dissipation and power wasted by digital circuits. It involves turning off the clock to certain parts of the digital design when not needed.
Verilog
1
star
17

Round-Robin-Arbiter-Fixed-Time-Sclices

Accessing a Memory location by multiple Processor. Arbiter takes four input requests and outputs a grant(ONE HOT ENCODED) signal.
Verilog
1
star
18

read_comments_as_HDL

using "AND" gate logic to test "read_comments_as_HDL" synthesis directive
Verilog
1
star
19

palindrome_3bit

You are tasked to design a circuit which would detect a 3-bit palindrome sequence from incoming stream of bits.
Verilog
1
star
20

generic_count_1

Generic counting one's in a Bus.
Verilog
1
star
21

leading_1_detector

Design a leading "1" detector circuit for 8-bit bus
Verilog
1
star
22

SPI

SPI is a synchronous communication protocol that transmits and receives information simultaneously with high data transfer rates and is designed for board-level communication over short distances. The SPI communication interface is advantageous when needing to communicate between multiple devices.
Verilog
1
star
23

Performance_Counter

This Verilog module named "counter" implements a configurable counter with a width parameter (WIDTH).
Verilog
1
star
24

Atomic-Counters

Question is in README
Verilog
1
star
25

Perfect_Square

This module is useful for generating perfect square values.
Verilog
1
star
26

Abhirecket

1
star
27

Programmable-Sequence-Detector

Programmable sequence detection refers to the ability to detect specific patterns or sequences of bits within a stream of data in a configurable or programmable manner.
Verilog
1
star
28

Div_5

Create a block that check if a number is divisible by “5” ? Every cycle, LSB receives a new bit; if the current sequence is divisible by “5”, block transmits “1”.
Verilog
1
star
29

fibanocci

The Fibonacci series is a sequence of numbers in which each number is the sum of the two preceding ones, usually starting with 0 and 1. So, the Fibonacci series begins as follows: 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233, 377, ...
Verilog
1
star