Laboratory for NanoIntegrated Systems (LNIS) (@lnis-uofu)
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lnis-uofu

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  • Stars
    star
    1,006
  • Global Org. Rank 15,268 (Top 5 %)
  • Registered over 4 years ago
  • Most used languages
    Verilog     43.3 %
    C
         16.7 %
    C++
         6.7 %
    HTML
         6.7 %
    Shell
         3.3 %
    Racket
         3.3 %
    MATLAB
         3.3 %
    Jupyter Notebook
         3.3 %
    SystemVerilog     3.3 %
    Python
         3.3 %
    SourcePawn     3.3 %
    HCL     3.3 %
  • Location ๐Ÿ‡บ๐Ÿ‡ธ United States
  • Country Total Rank 8,685
  • Country Ranking
    Verilog     5
    SourcePawn     63
    SystemVerilog     331
    Racket
         388
    HCL     1,404
    Shell
         3,199
    HTML
         5,362
    C
         7,936
    MATLAB
         8,738

Top repositories

1

OpenFPGA

An Open-source FPGA IP Generator
Verilog
829
star
2

SOFA

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
Verilog
128
star
3

LSOracle

IDEA project source files
Verilog
93
star
4

TIGFET-10nm-PDK

An open source PDK using TIGFET 10nm devices.
Shell
42
star
5

JPEG_LS

Verilog
19
star
6

FreePDK45-RRAM-Addon

A RRAM addon for the NCSU FreePDK 45nm
HTML
18
star
7

yosys_prefix_trees

Yosys plugin for optimized adders using tdene/synth_opt_adders utility
C++
9
star
8

TIGFET-10nm-SCLIB

An open source standard cell library using TIGFET 10nm devices.
SourcePawn
7
star
9

ML-Mapper

C
7
star
10

Caravel-QLAP3

Verilog
5
star
11

Caravel-SOFA-CHD

Verilog
5
star
12

SOFA-Plus-eFPGA

SOFA-Plusis second version of SOFA eFPGA series. This is Heterogeneous eFPGA with enhanced DSP features.
Verilog
5
star
13

FPGA_Secured_Bitstream

eFGPA IP to decode on-the-fly an encrypted bitstream for different configuration protocol
Verilog
4
star
14

MemoryCharacterizationSystem

An FPGA-based low-cost RRAM test system.
HTML
3
star
15

CMOS_RRAM_Addon

A design kit add-on for hybrid CMOS-RRAM full-custom exploration. This add-on can be used with any commercial CMOS design kits.
HCL
3
star
16

Caravel-QLSOFA-HD

Verilog
3
star
17

ECE_5710_6710_F23

University of Utah ECE 6710/5710 Lab Material
Verilog
2
star
18

tsmc_template

Verilog
2
star
19

LSOracle-Plugin

Yosys Plugin for LSOracle
C++
2
star
20

T3-DNN

T3: Tiny Time-series Transformer Deep Neural Network architecture
Jupyter Notebook
2
star
21

testchip_4t1r

RRAM testchip designed to evaluate 4t1r configuration. Official submission repository for google MPW4 tapeout program.
Verilog
2
star
22

GF12_template

Verilog
1
star
23

FROG_test_infrastructure

C
1
star
24

MPack

A packing tool to handle matrix-based FPGAs (MClusters) organization.
C
1
star
25

OpenFPGA-Softcores

Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations
Python
1
star
26

embedded-systems-template

C
1
star
27

skywater_template

SystemVerilog
1
star
28

LSOracle-Plugin-packaging

1
star
29

FPGA_Benchmark_Suite

Modern industrial benchmark suite to evaluate FPGA architecture performance, tool performance, and enable FPGA architecture exploration.
1
star
30

ASOracle

Racket
1
star
31

AirU

NSF-funded low-cost pollution monitoring network
C
1
star
32

TIGFET-BCB

A system-level evaluation of TIGFETs using the BCB3.0 methodology from Intel.
MATLAB
1
star