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Harvard Architecture, Circuits, and Compilers (@harvard-acc)

harvard-acc

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gem5-aladdin

End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.

ALADDIN

A pre-RTL, power-performance model for fixed-function accelerators

LLVM-Tracer

An LLVM pass to profile dynamic LLVM IR instructions and runtime values

DeepRecSys

http://vlsiarch.eecs.harvard.edu/research/recommendation/

smaug

SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin

EdgeBERT

HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference

FlexASR

FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks

RecPipe

ESP_Systolic_Array_Accelerator