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@SpinalHDL

SpinalHDL

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41.7 %

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VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

SpinalHDL

Scala based HDL

NaxRiscv

SaxonSoc

SoC based on VexRiscv and ICE40 UP5K

SpinalWorkshop

Labs to learn SpinalHDL

SpinalTemplateSbt

A basic SpinalHDL project

VexRiscvSoftcoreContest2018

SpinalCrypto

SpinalHDL - Cryptography libraries

VexiiRiscv

SpinalDoc

SpinalHDL documentation assets (pictures, slides, ...)

VexRiscvSocSoftware

SpinalDoc-RTD

The sources of the online SpinalHDL doc

CocotbLib

SpinalBaseProject-OLD-

rvls

RISCV lock-step checker based on Spike

NaxSoftware

SpinalTemplateSbtDependencies

An SpinalHDL project example which use VexRiscv git as a dependency

SpinalTemplateGradle

A basic SpinalHDL project, configured with Gradle instead of SBT

docker

SpinalNomad

NaxRiscv-Rtd

buildroot-spinal-saxon

VexRiscvRegressionData

Used to store heavy data required to run full VexRiscv regressions

VexiiRiscv-RTD