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@SpinalHDL

SpinalHDL

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Registered almost 10 years ago
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Scala
41.7 %

Python
16.7 %

C
12.5 %

Assembly
8.3 %

Dockerfile
8.3 %

HTML
4.2 %

C++
4.2 %

Verilog 4.2 %

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

SpinalHDL

Scala based HDL

NaxRiscv

SaxonSoc

SoC based on VexRiscv and ICE40 UP5K

SpinalWorkshop

Labs to learn SpinalHDL

VexiiRiscv

Like VexRiscv, but, Harder, Better, Faster, Stronger

SpinalTemplateSbt

A basic SpinalHDL project

VexRiscvSoftcoreContest2018

SpinalCrypto

SpinalHDL - Cryptography libraries

SpinalDoc

SpinalHDL documentation assets (pictures, slides, ...)

VexRiscvSocSoftware

SpinalDoc-RTD

The sources of the online SpinalHDL doc

CocotbLib

SpinalBaseProject-OLD-

rvls

RISCV lock-step checker based on Spike

NaxSoftware

SpinalTemplateSbtDependencies

An SpinalHDL project example which use VexRiscv git as a dependency

docker

SpinalTemplateGradle

A basic SpinalHDL project, configured with Gradle instead of SBT

SpinalNomad

NaxRiscv-Rtd

buildroot-spinal-saxon

VexRiscvRegressionData

Used to store heavy data required to run full VexRiscv regressions

VexiiRiscv-RTD