Chair of Electronic Design Automation (@RPTU-EIS)
Guthub

RPTU-EIS

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  • Stars
    star
    48
  • Global Org. Rank 81,194 (Top 26 %)
  • Followers 6
  • Registered over 3 years ago
  • Most used languages
    SystemVerilog     37.5 %
    Verilog     25.0 %
    C
         12.5 %
    Scala
         12.5 %
    C++
         12.5 %
  • Location 🇩🇪 Germany
  • Country Total Rank 25,480
  • Country Ranking
    SystemVerilog     7
    Verilog     28
    Scala
         735
    C
         2,030
    C++
         5,324

Top repositories

1

upec-boom-verification-suite

This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.
Verilog
15
star
2

RISCV-Core

5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
C
11
star
3

SecureBOOM

Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)
Verilog
5
star
4

VDSProject

This repository contains the basic files for the class project of the course "Verification of Digital Systems"
C++
4
star
5

symbolic-pmp

This repository contains a symbolic and secure configuration template for the RISC-V Physical Memory Protection (PMP) to be used in SV/SVA based verification flows.
SystemVerilog
3
star
6

UPEC-DIT

This repository contains experiments and results on using UPEC to prove data-independent timing in hardware.
3
star
7

ADSProject

This repository contains the basic files for the class project of the course "Architecture of Digital Systems I"
Scala
2
star
8

OpenTitan_with_Access_Control

OpenTitan Silver Release v5 copy for security improvements
SystemVerilog
2
star
9

Security-Conscious-Hardware

Collection of experiments on data-oblivious hardware designs that dynamically adjust their latency
SystemVerilog
1
star