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HPC Lab (@HPC-Lab-IITB)

HPC-Lab-IITB

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Bluespec 1

VHDL 84

Verilog 281

Clarinet

A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating custom functional units like posit arithmetic units.

Melodica

A posit arithmetic unit which implements Quire. Designed to be used both as a functional unit or as a tightly coupled accelerator.

HOG-SVM

ISA-Power-Benchmarks

The aim is to do a power analysis of each RISC-V instruction, such that in the future an extremely superior RISC-V ISA core can be designed, that can give the best performance in both prospective -> highest speed during the execution of any task along with the LOWEST POWER CONSUMPTION as well.