Chair for Security Engineering (@Chair-for-Security-Engineering)
Guthub

Chair-for-Security-Engineering

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  • Stars
    star
    146
  • Global Org. Rank 47,819 (Top 16 %)
  • Registered over 4 years ago
  • Most used languages
    Verilog     33.3 %
    VHDL     29.6 %
    C
         18.5 %
    C++
         7.4 %
    Python
         3.7 %
    Cuda     3.7 %
    SystemVerilog     3.7 %
  • Location πŸ‡©πŸ‡ͺ Germany
  • Country Total Rank 10,143
  • Country Ranking
    SystemVerilog     10
    Verilog     11
    VHDL     18
    Cuda     30
    C
         1,164
    C++
         5,729
    Python
         6,870

Top repositories

1

AGEMA

Automated Generation of Masked Hardware
Verilog
15
star
2

AES_masked_BRAM

Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
Verilog
14
star
3

BIKE

Contains HDL code for the PQC Key Encapsulation Mechanism BIKE
VHDL
13
star
4

VERICA

Verilog
12
star
5

SILVER

SILVER - Statistical Independence and Leakage Verification
C
12
star
6

DL-LA

DL-LA: Deep Learning Leakage Assessment. Source Code and Traces.
Python
11
star
7

FIVER

Verilog
9
star
8

KEM-NIZKPoP

Proof-of-possession for KEM certificates using verifiable generation
C
8
star
9

ecmongpu

ECM Factorization on CUDA-GPUs
Cuda
8
star
10

dilithium-artix7

Implementations for all round-3 parameter sets of the PQC signature scheme Dilithium
VHDL
7
star
11

LWC-Masking

Verilog
6
star
12

RacingBIKE

SystemVerilog
5
star
13

NullFresh

Codes and designs of first-order SCA secure hardware implementations without fresh randomness
Verilog
4
star
14

Write-Write

PoC Code from the Paper "Write Me and I'll Tell You Secrets - Write-After-Write Effects On Intel CPUs"
C
4
star
15

XMSS-LMS-HW-Agile

Code for the paper "Agile Acceleration of Stateful Hash-Based Signatures in Hardware"
VHDL
3
star
16

SPEEDY

Code repository for the SPEEDY family of ultra low-latency block ciphers
VHDL
2
star
17

XMSS-VHDL

Configurable Hardware Implementation of XMSS
VHDL
2
star
18

SAIREDA

Security-Aware Intermediate Representation and Electronic Design Automation
C++
2
star
19

Low-Latency_Keccak

Verilog
1
star
20

FrodoKEM

Hardware Implementation of FrodoKEM
VHDL
1
star
21

GHPC

Generic Hardware Private Circuits
VHDL
1
star
22

lattice-anonymous-credentials

C
1
star
23

HPC3

Verilog
1
star
24

Combined-Threshold-Implementation

Implementations for CTI evaluation
Verilog
1
star
25

EASIMask

VHDL
1
star
26

dilithium-faults

C
1
star
27

NullFresh2

Codes and designs of second-order SCA secure hardware implementations with almost no fresh randomness
C++
1
star